? semiconductor components industries, llc, 2001 june, 2001 rev. 2 1 publication order number: mc100ep14/d mc100ep14 3.3v / 5v1:5 differential ecl/pecl/hstl clock driver the mc100ep14 is a low skew 1to5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. the ecl/pecl input signals can be either differential or singleended (if the v bb output is used). hstl inputs can be used when the lvep14 is operating under pecl conditions. the ep14 specifically guarantees low outputtooutput skew. optimal design, layout, and processing minimize skew within a device and from device to device. to ensure that the tight skew specification is realized, both sides of any differential output need to be terminated even if only one output is being used. if an output pair is unused, both outputs may be left open (unterminated) without affecting skew. the common enable (en ) is synchronous, outputs are enabled/ disabled in the low state. this avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. the mc100ep14, as with most other ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the ep14 to be used for high performance clock distribution in 5.0 v systems. designers can take advantage of the ep14's performance to distribute low skew clocks across the backplane or the board. ? 400 ps typical propagation delay ? 100 ps devicetodevice skew ? 25 ps within device skew ? maximum frequency > 2 ghz typical ? the 100 series contains temperature compensation ? pecl and hstl mode: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state http://onsemi.com device package shipping ordering information mc100ep14dt tssop 75 units/tray mc100ep14dtr2 tssop 2500 tape & reel tssop20 dt suffix case 948e marking diagram* a = assembly location l = wafer lot y = year w = work week *for additional information, see application note and8002/d 100 ep14 alyw 20 1 20 1
mc100ep14 http://onsemi.com 2 figure 1. 20lead pinout (top view) and logic diagram warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description function ecl/pecl/hstl clk input ecl/pecl/hstl clk input ecl/pecl outputs ecl/pecl active clock select input ecl sync enable reference voltage output positive supply negative supply pin clk0*, clk0 ** clk1*, clk1 ** q0:4, q0:4 clk_sel* en * vbb vcc vee q2 q1 q3 q1 17 18 16 15 14 13 12 4 3 5678 9 11 10 clk1 clk0 clk0 q0 19 20 2 1 en q2 q0 q3 q4 q4 clk1 10 d q clk0 l h x x x clk1 x x l h x clk_sel l l h h x en l l l l h q l h l h l* function table * on next negative transition of clk0 or clk1 v cc v cc v bb v ee clk_sel * pins will default low when left open. ** pins will default to v cc /2 when left open. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 357 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc100ep14 http://onsemi.com 3 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 20 tssop 20 tssop 140 100 c/w c/w q jc thermal resistance (junction to case) std bd 20 tssop 23 to 41 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 65 75 58 68 78 62 72 82 ma v oh output high voltage (note 4) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 4) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (single ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 5) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 65 75 58 68 78 62 72 82 ma v oh output high voltage (note 7) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 7) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (single ended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single ended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential) (note 8) 1.2 5.0 1.2 5.0 1.2 5.0 v i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. all loading with 50 ohms to v cc 2.0 volts. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100ep14 http://onsemi.com 4 100ep dc characteristics, necl v cc = 0 v; v ee = 5.5 v to 3.0 v (note 9) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 65 75 58 68 78 62 72 82 ma v oh output high voltage (note 10) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 10) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (single ended) 1225 880 1225 880 1225 880 mv v il input low voltage (single ended) 1945 1625 1945 1625 1945 1625 mv v bb output reference voltage 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 11) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current 150 150 150 m a i il input low current clk clk 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 ohms to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 12) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max lvpecl /hstl maximum frequency (see figure 2. f max /jitter) > 2 > 2 > 2 ghz t plh t phl propagation delay to output differential 275 330 400 275 375 450 400 475 600 ps t skew withindevice skew devicetodevice skew (note 13) 25 100 35 125 30 150 45 175 40 175 50 200 ps t s t h setup time to clk en to clk hold time en to clk 100 200 50 140 100 200 50 140 100 200 50 140 ps t jitter cycletocycle jitter (see figure 2. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r /t f output rise/fall time (20%80%) 140 180 240 145 200 270 150 225 300 ps 12. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v. 13. skew is measured between outputs under identical transitions.
mc100ep14 http://onsemi.com 5 0 100 200 300 400 500 600 700 800 900 0 1000 2000 3000 4000 1 2 3 4 5 6 7 8 9 figure 2. f max /jitter frequency (mhz) (jitter) v outpp (mv) jitter out ps (rms) v tt = v cc 2.0 v driver device receiver device q qb d db 50 50 v tt figure 3. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc100ep14 http://onsemi.com 6 package dimensions tssop20 dt suffix plastic tssop package case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-.
mc100ep14 http://onsemi.com 7 notes
mc100ep14 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ep14/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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